1. Field of the Invention
The present invention relates to logic circuit representation; in particular, the present invention relates to a logic circuit representation which includes executable code that can be linked into a computer-aided design tool for simulation or verification.
2. Discussion of the Related Art
Conventional logic simulation tools and their associated hardware description languages (HDLs), which are often designed to accommodate a large number of diversed design styles, are not efficient in handling such complex logic circuits microprocessors. The overhead cost, i.e. the complexity of the simulator code and the associated memory requirements, renders these simulators too slow and requiring too much memory for handling the complexity of a microprocessor or a similar complex logic circuit.
In a conventional logic design methodology, a designer partitions a logic circuit under design into a hierarchy of functional blocks. Using a procedural programming language, such as the "C" language, well-known to those skilled in the art, the designer then writes simulation procedures for each functional block. Typically, in such a hierarchy, the lowest level procedures each compute a register transfer level (RTL) behavior of a small logic circuit. Simulation is achieved by executing this hierarchy of procedures for all clock periods during a prescribed simulation period. A design achieved with the help of such a simulation is then used to create a HDL description of the logic circuit. From this HDL description, an actual implementation of the logic circuit can be obtained using well-known methods, such as a logic synthesis tool. Because a conventional programming language does not provide data structures similar to those provided by a hardware description language, e.g. multiple instantiations of a circuit element, or a data structure customized for representing both an individual binary logic signal and a bus, creating an HDL description from these simulation procedures is often an undesirably complex and error-prone task.
Alternatively, simulation can be performed using an interpreter of the HDL used in the logic design. Many such interpreters are available, including those interpreting the Verilog HDL, well-known to those skilled in the art. However, in these simulators, since the HDL description is interpreted, the resulting simulation is too slow for use at the beginning stages of a design, when different design options are often simulated to provide a basis for a design decision. Thus, there is a need for a method for constructing logic simulation models which are expressed in data structures similar to those provided in HDLs and, at the same time, capable of being compiled with a simulator for simulation in a digital computer.